The RX Subsystem has three AXI interfaces. This allows the user to optimize the clock buffer resources. The transceivers convert the parallel data into serial and vice versa. The transceiver module incorporates the high speed GT transceivers. The RX Subsystem module extracts the video and audio streams from the HDMI stream.

The HDMI Transceiver (GTX) module receives the serial RX data and converts it into a parallel data stream. The HDMI RX subsystem consists of two major modules.

Xilinx provides IP suite for HDMI system for 7 series FPGA family, which consists of HDMI Tranceiver (GTX), HDMI Receiver (RX) and HDMI Transmitter (TX) subsystems.

Xilinx LogiCore IPs for HDMI system, Video processing IP sub-blocksĪpart from these major components, other peripheral IPs like DDR3 memory controller (MIG from Xilinx for PL memory or In-built controller within PS for PS_DDR), Ethernet MAC IPs are also used.

Video processing subsystem for pre/post processing such as color space conversion, video, scaling, chroma subsampling features Īs shown in Fig 1, the hardware implementation consists of 3 major components.

Video quality at 0.99% SSIM, or 50dB PSNR or higher.

Variable bit rate (VBR) and constant bit rate (CBR) support.

HDMI2.0 Receiver and Transmitter subsystem integrated.

H.264 Intra-only Hi422 Level 5.1 encoder and decoder.

Complete Modular implementation with scope for customization and scalability.

This is ready to tape-out SoC solution allowing customer specific customizations in SW, hence significantly reducing time to market turn around.įig: Block Diagram of Atria Logic UHD H.264 Codec Solution The proposed solution differentiates in terms of SW friendly approach with full fledged Linux OS and application drivers running on ARM Cortex A9 processor. There are many previous works with hardware-only implementation. In this article, architecture and implementation of UHD H.264/AVC codec IP SoC solution with Atria Logic feature rich, low latency, high video quality H.264 (AVC) UHD Hi422 Intra H.264 codec IP plus highly efficient Xilinx LogiCore HDMI subsystem IPs is described. This creates a big challenge for efficient hardware and/or software implementations. The H.264/AVC video coding standard achieves a significant improvement in coding efficiency with increased computational complexity relative to former standards. Numerous industries in broadcast, cable, videoconferencing and consumer electronics space are using H.264 as the video codec of choice for their products and services. By Anand V Kulkarni, Senior Engineering Manager, Atria Logic, Bangalore, India

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